Various imager circuits have been proposed such as charge coupled device (CCD) arrays, complementary metal oxide semiconductor (CMOS) arrays, arrays combining both CCD and CMOS features, as well as hybrid infrared focal-plane arrays (IR-FPAs). Conventional arrays have pixels containing a light-sensing element, e.g. a photodiode and readout circuitry that outputs signals indicative of the light sensed by the pixels.
A CMOS imager, for example, includes a focal plane array of pixel cells; each cell includes a photodetector (e.g., a photogate, photoconductor or a photodiode) overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a storage region, connected to the gate of the source follower transistor. Charge generated by the photodetector is sent to the storage region. The imager may also include a transistor for transferring charge from the photodetector to the storage region and another transistor for resetting the storage region to a predetermined charge level prior to charge transference.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524 and 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
FIG. 1 illustrates a block diagram of a CMOS imager device 100 having a pixel array 105 with each pixel cell being constructed as described above, or as other known pixel cell circuits. Pixel array 105 comprises a plurality of pixels arranged in a predetermined number of columns and rows (not shown). The pixels of each row in array 105 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for the entire array 105. The row lines are selectively activated in sequence by a row driver 110 in response to row address decoder 115. The column select lines are selectively activated in sequence for each row activation by a column driver 120 in response to column address decoder 125. Thus, a row and column address is provided for each pixel.
The CMOS imager 100 is operated by a control circuit 130, which controls address decoders 115, 125 for selecting the appropriate row and column lines for pixel readout. Control circuit 130 also controls the row and column driver circuitry 110, 120 so that they apply driving voltages to the drive transistors of the selected row and column lines. The pixel output signals typically include a pixel reset signal Vrst taken off of the storage region when it is reset by the reset transistor and a pixel image signal Vsig, which is taken off the storage region after photo-generated charges are transferred to it. The Vrst and Vsig signals are read by a sample and hold circuit 135 and are subtracted by a differential amplifier 140, to produce a differential signal Vrst-Vsig for each pixel. Vrst-Vsig represents the amount of light impinging on the pixels. This difference signal is digitized by an analog-to-digital converter 145. The digitized pixel signals are fed to an image processor 150 to form a digital image output. The digitizing and image processing can be located on or off the imager chip. In some arrangements the differential signal Vrst-Vsig can be amplified as a differential signal and directly digitized by a differential analog to digital converter.
FIG. 2 illustrates a four transistor (4T) CMOS imager pixel cell 200. Pixel cell 200 includes a photodiode 205 connected to a transfer transistor 225. The transfer transistor 225 is also connected to a storage region 220, which may be constructed as a floating diffusion region. A reset transistor 230, a capacitor 215 and a gate of a source follower transistor 240 are connected to storage region 220. A row select transistor 235 is connected to source follower transistor 240. The active elements of pixel cell 200 perform the functions of (1) photon to charge conversion by photodiode 205; (2) resetting the storage region to a known state before the transfer of charge to it by reset transistor 230; (3) transfer of charge to the storage region 220 by the transfer transistor 225; (4) selection of the cell 200 for readout by row select transistor 235; and (5) output and amplification of a signal representing a reset voltage (i.e., Vrst) and a pixel signal voltage (i.e., Vsig) based on the charges present on storage region 220 by source follower transistor 240. Capacitor 215 is utilized because charges produced during an integration period by photodiode 205 may be greater than the capacity of storage region 220. Accordingly, capacitor 215 provides additional charge storage capacity. The pixel cell 200 of FIG. 2 is formed on a semiconductor substrate as part of an imager device pixel array (e.g., array 105 of FIG. 1).
Since transfer transistor 225 is positioned between photodiode 205 and storage region 220, the storage region 220 can be reset prior to transferring electrons to it from the photo diode 205. This permits a correlated double sampling operation resulting in reduced kTC noise and image noise.
With the pixel circuit configuration of FIG. 2 during reset, in order to obtain a maximum voltage swing at storage region 220, the reset transistor drain voltage is boosted to Vpix (voltage source 210)+Vt(a threshold voltage drop of reset transistor 230). By adding voltage Vt to the reset voltage as applied to the storage region 220, the storage region 220 can be reset to Vpix allowing a greater output signal swing in the signal produced by the source follower transistor 240 in response to charges transferred to the storage region 220 from photodiode 205. This technique requires additional supply voltage boost circuits to boost the supply voltage for reset which increases the size, power consumption, design complexity and costs of the pixel and associated circuit.